This invention relates in general to duplex digital systems and more particularly to a cross-copy arrangement for synchronizing parity clock signals between the active and standby copies of a duplex digital system.
A typical duplex system employs duplicated peripheral processors containing identical data and operating synchronously to control a simplex or an individual controlled stage. One of the peripheral processors is normally used as the active copy while the other is left in a standby status. Since both copies contain identical information and are running synchronously the standby copy may be brought on line replacing the active copy in the event the active copy processor fails.
Therefore, in response to read or write commands from each processor the controlled stage transmits information simultaneously to both stages.
It is not uncommon in such systems that timing skew between the two copies of the system allows one copy to run faster than the other. If the timing skew causes the standby copy to run faster than the active copy, returned data information to the active copy from the controlled stage can cause a false error signal. The returned data information normally includes a parity bit, which, because of the timing skew would be clocked too soon in the standby copy than in the active copy generating a false parity failure.
Therefore, the present invention synchronizes the parity clock signal between the active and standby copies of a duplex digital system preventing false parity failures.